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Preliminary Rev. 0.95 8/11 Copyright © 2011 by Silicon Laboratories Si5351A/B/C
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si5351A/B/C
I
2
C-PROGRAMMABLE ANY-FREQUENCY CMOS CLOCK
GENERATOR + VCXO
Features
Applications
Description
The Si5351 is an I
2
C configurable clock generator that is ideally suited for replacing
crystals, crystal oscillators, VCXOs, phase-locked loops (PLLs), and fanout buffers in
cost-sensitive applications. Based on a PLL/VCXO + high resolution MultiSynth fractional
divider architecture, the Si5351 can generate any frequency up to 160 MHz on each of its
outputs with 0 ppm error. Three versions of the Si5351 are available to meet a wide
variety of applications. The Si5351A generates up to 8 free-running clocks using an
internal oscillator for replacing crystals and crystal oscillators. The Si5351B adds an
internal VCXO and provides the flexibility to replace both free-running clocks and
synchronous clocks. The Si5351B eliminates the need for higher cost, custom pullable
crystals while providing reliable operation over a wide tuning range. The Si5351C offers
the same flexibility but synchronizes to an external reference clock (CLKIN).
Functional Block Diagram
Generates up to 8 non-integer-related
frequencies from 8 kHz to 160 MHz
I
2
C user definable configuration
Exact frequency synthesis at each output
(0 ppm error)
Highly linear VCXO
Optional clock input (CLKIN)
Low output period jitter: 100 ps pp
Configurable spread spectrum selectable
at each output
Operates from a low-cost, fixed frequency
crystal: 25 or 27 MHz
Supports static phase offset
Programmable rise/fall time control
Glitchless frequency changes
Separate voltage supply pins:
Core VDD: 2.5 or 3.3 V
Output VDDO: 1.8, 2.5, or 3.3 V
Excellent PSRR eliminates external
power supply filtering
Very low power consumption
Adjustable output-output delay
Available in 3 packages types:
10-MSOP: 3 outputs
24-QSOP: 8 outputs
20-QFN (4x4 mm): 8 outputs
PCIE Gen 1 compliant
Supports HCSL compatible swing
HDTV, DVD/Blu-ray, set-top box
Audio/video equipment, gaming
Printers, scanners, projectors
Residential gateways
Networking/communication
Servers, storage
XO replacement
Si5351A
Multi
Synth
N
N = 2 or 7
I
2
C
SSEN
OEB
Multi
Synth
0
Multi
Synth
1
Si5351B
PLL
VC
VCXO
I
2
C
SSEN
OEB
Multi
Synth
0
Multi
Synth
1
Multi
Synth
2
Multi
Synth
3
Multi
Synth
4
Multi
Synth
5
Multi
Synth
6
Multi
Synth
7
Si5351C
PLLA
CLKIN
PLLB
I
2
C
INTR
OEB
Multi
Synth
0
Multi
Synth
1
Multi
Synth
2
Multi
Synth
3
Multi
Synth
4
Multi
Synth
5
Multi
Synth
6
Multi
Synth
7
XA
XB
OSC
XA
XB
OSC
PLLB
PLLA
XA
XB
OSC
Ordering Information:
See page 66
10-MSOP
24-QSOP
20-QFN
Seitenansicht 0
1 2 3 4 5 6 ... 71 72

Inhaltsverzeichnis

Seite 1 - Si5351A/B/C

Preliminary Rev. 0.95 8/11 Copyright © 2011 by Silicon Laboratories Si5351A/B/CThis information applies to a product under development. Its characteri

Seite 2

Si5351A/B/C10 Preliminary Rev. 0.95Figure 2. Block Diagrams of Si5351B and Si5351C 8-Output DevicesOSCXAXBPLLVCXOR0R1CLK0CLK1VDDOAR2R3CLK2CLK3VDDOBR4R

Seite 3 - TABLE OF CONTENTS

Si5351A/B/CPreliminary Rev. 0.95 113. Functional DescriptionThe Si5351 is a versatile I2C programmable clock generator that is ideally suited for rep

Seite 4

Si5351A/B/C12 Preliminary Rev. 0.953.1.2. External Clock Input (CLKIN)The external clock input is used as a clock reference for the PLLs when generati

Seite 5

Si5351A/B/CPreliminary Rev. 0.95 133.4. Spread SpectrumSpread spectrum can be enabled on any of the clock outputs that use PLLA as its reference. Spr

Seite 6

Si5351A/B/C14 Preliminary Rev. 0.954. I2C InterfaceMany of the functions and features of the Si5351 are controlled by reading and writing to the RAM

Seite 7

Si5351A/B/CPreliminary Rev. 0.95 15Figure 9. I2C Write OperationA read operation is performed in two stages. A data write is used to set the register

Seite 8

Si5351A/B/C16 Preliminary Rev. 0.955. Configuring the Si5351The Si5351 is a highly flexible clock generator which is entirely configurable through it

Seite 9

Si5351A/B/CPreliminary Rev. 0.95 17Figure 12. I2C Programming ProcedureDisable OutputsSet CLKx_DIS high; Reg. 3 = 0xFFPowerdown all output driversReg.

Seite 10

Si5351A/B/C18 Preliminary Rev. 0.955.2. Si5351 Application ExamplesThe Si5351 is a versatile clock generator which serves a wide variety of applicati

Seite 11

Si5351A/B/CPreliminary Rev. 0.95 195.4. Replacing Crystals, Crystal Oscillators, and VCXOsThe Si5351B combines free-running clock generation and a VC

Seite 12

Si5351A/B/C2 Preliminary Rev. 0.95

Seite 13

Si5351A/B/C20 Preliminary Rev. 0.955.6. Replacing a Crystal with a ClockThe Si5351 can be driven with a clock signal through the XA input pin.Figure

Seite 14

Si5351A/B/CPreliminary Rev. 0.95 216. Design ConsiderationsThe Si5351 is a self-contained clock generator that requires very few external components.

Seite 15

Si5351A/B/C22 Preliminary Rev. 0.956.6. Trace CharacteristicsThe Si5351A/B/C features various output current drives ranging from 2 to 8 mA (default).

Seite 16

Si5351A/B/CPreliminary Rev. 0.95 237. Register Map SummaryThe following is a summary of the register map used to read status, control, and configure

Seite 17

Si5351A/B/C24 Preliminary Rev. 0.9566 MS3_P3[15:8]67 MS3_P3[7:0]68 R3_DIV[2:0] MS3_P1[17:16]69 MS3_P1[15:8]70 MS3_P1[7:0]71 MS3_P3[19:16] MS3_P2[19:16

Seite 18

Si5351A/B/CPreliminary Rev. 0.95 258. Register DescriptionsReset value = 0000 0000 Register 0. Device StatusBitD7D6D5D4D3D2D1D0NameSYS_INIT LOL_B LOL

Seite 19 - Preliminary Rev. 0.95 19

Si5351A/B/C26 Preliminary Rev. 0.95Reset value = 0000 0000 Register 1. Interrupt Status StickyBit D7 D6 D5 D4 D3D2D1D0NameSYS_INIT_STKY LOL_B_STKY LOL

Seite 20 - 20 Preliminary Rev. 0.95

Si5351A/B/CPreliminary Rev. 0.95 27Reset value = 0000 0000 Register 2. Interrupt Status MaskBit D7 D6 D5 D4 D3D2D1D0NameSYS_INIT_MASK LOL_B_MASK LOL_A

Seite 21 - Preliminary Rev. 0.95 21

Si5351A/B/C28 Preliminary Rev. 0.95Reset value = 0000 0000Reset value = 0000 0000 Register 3. Output Enable ControlBitD7D6D5D4D3D2D1D0NameCLK7_OEB CLK

Seite 22 - 22 Preliminary Rev. 0.95

Si5351A/B/CPreliminary Rev. 0.95 29Reset value = 0000 0000 Register 15. PLL Input Source BitD7D6D5D4D3D2D1D0NamePLLB_SRC PLLA_SRCTypeR/W R/W R/W R/W R

Seite 23 - Preliminary Rev. 0.95 23

Si5351A/B/CPreliminary Rev. 0.95 3TABLE OF CONTENTSSection Page1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Seite 24 - 24 Preliminary Rev. 0.95

Si5351A/B/C30 Preliminary Rev. 0.95Reset value = 0000 0000 Register 16. CLK0 Control BitD7D6D5D4D3D2D1D0NameCLK0_PDN MS0_INT MS0_SRC CLK0_INV CLK0_SRC

Seite 25 - BitD7D6D5D4D3D2D1D0

Si5351A/B/CPreliminary Rev. 0.95 31Reset value = 0000 0000 Register 17. CLK1 Control BitD7D6D5D4D3D2D1D0NameCLK1_PDN MS1_INT MS1_SRC CLK1_INV CLK1_SRC

Seite 26 - Bit D7 D6 D5 D4 D3D2D1D0

Si5351A/B/C32 Preliminary Rev. 0.95Reset value = 0000 0000 Register 18. CLK2 Control BitD7D6D5D4D3D2D1D0NameCLK2_PDN MS2_INT MS2_SRC CLK2_INV CLK2_SRC

Seite 27 - Preliminary Rev. 0.95 27

Si5351A/B/CPreliminary Rev. 0.95 33Reset value = 0000 0000 Register 19. CLK3 Control BitD7D6D5D4D3D2D1D0NameCLK3_PDN MS3_INT MS3_SRC CLK3_INV CLK3_SRC

Seite 28

Si5351A/B/C34 Preliminary Rev. 0.95Reset value = 0000 0000 Register 20. CLK4 Control BitD7D6D5D4D3D2D1D0NameCLK4_PDN MS4_INT MS4_SRC CLK4_INV CLK4_SRC

Seite 29 - Preliminary Rev. 0.95 29

Si5351A/B/CPreliminary Rev. 0.95 35Reset value = 0000 0000 Register 21. CLK5 Control BitD7D6D5D4D3D2D1D0NameCLK5_PDN MS5_INT MS5_SRC CLK5_INV CLK5_SRC

Seite 30 - 30 Preliminary Rev. 0.95

Si5351A/B/C36 Preliminary Rev. 0.95Reset value = 0000 0000 Register 22. CLK6 Control BitD7D6D5D4D3D2D1D0NameCLK6_PDN FBA_INT MS6_SRC CLK6_INV CLK6_SRC

Seite 31 - Preliminary Rev. 0.95 31

Si5351A/B/CPreliminary Rev. 0.95 37Reset value = 0000 0000 Register 23. CLK7 Control BitD7D6D5D4D3D2D1D0NameCLK7_PDN FBB_INT MS7_SRC CLK7_INV CLK7_SRC

Seite 32 - 32 Preliminary Rev. 0.95

Si5351A/B/C38 Preliminary Rev. 0.95Reset value = 0000 0000Reset value = 0000 0000 Register 24. CLK3–0 Disable StateBitD7D6D5D4D3D2D1D0NameCLK3_DIS_STA

Seite 33 - Preliminary Rev. 0.95 33

Si5351A/B/CPreliminary Rev. 0.95 39Reset value = xxxx xxxxReset value = xxxx xxxxRegister 42. Multisynth0 ParametersBitD7D6D5D4D3D2D1D0NameMS0_P3[15:8

Seite 34 - 34 Preliminary Rev. 0.95

Si5351A/B/C4 Preliminary Rev. 0.951. Electrical SpecificationsTable 1. Recommended Operating ConditionsParameter Symbol Test Condition Min Typ Max Un

Seite 35 - Preliminary Rev. 0.95 35

Si5351A/B/C40 Preliminary Rev. 0.95Reset value = xxxx xxxxReset value = xxxx xxxxRegister 44. Multisynth0 ParametersBitD7D6D5D4D3D2D1D0Name R0_DIV[2:0

Seite 36 - 36 Preliminary Rev. 0.95

Si5351A/B/CPreliminary Rev. 0.95 41Reset value = xxxx xxxxReset value = xxxx xxxxReset value = xxxx xxxxRegister 46. Multisynth0 ParametersBitD7D6D5D4

Seite 37 - Preliminary Rev. 0.95 37

Si5351A/B/C42 Preliminary Rev. 0.95Reset value = xxxx xxxxReset value = xxxx xxxxReset value = xxxx xxxxRegister 49. Multisynth0 ParametersBitD7D6D5D4

Seite 38

Si5351A/B/CPreliminary Rev. 0.95 43Reset value = xxxx xxxxReset value = xxxx xxxxRegister 52. Multisynth1 ParametersBitD7D6D5D4D3D2D1D0NameR1_DIV[2:0]

Seite 39 - Preliminary Rev. 0.95 39

Si5351A/B/C44 Preliminary Rev. 0.95Reset value = xxxx xxxxReset value = xxxx xxxxReset value = xxxx xxxxRegister 54. Multisynth1 ParametersBitD7D6D5D4

Seite 40 - 40 Preliminary Rev. 0.95

Si5351A/B/CPreliminary Rev. 0.95 45Reset value = xxxx xxxxReset value = xxxx xxxxReset value = xxxx xxxxRegister 57. Multisynth1 ParametersBitD7D6D5D4

Seite 41 - Preliminary Rev. 0.95 41

Si5351A/B/C46 Preliminary Rev. 0.95Reset value = xxxx xxxxReset value = xxxx xxxxRegister 60. Multisynth2 ParametersBitD7D6D5D4D3D2D1D0Name R2_DIV[2:0

Seite 42 - 42 Preliminary Rev. 0.95

Si5351A/B/CPreliminary Rev. 0.95 47Reset value = xxxx xxxxReset value = xxxx xxxxReset value = xxxx xxxxRegister 62. Multisynth2 ParametersBitD7D6D5D4

Seite 43 - Preliminary Rev. 0.95 43

Si5351A/B/C48 Preliminary Rev. 0.95Reset value = xxxx xxxxReset value = xxxx xxxxReset value = xxxx xxxxRegister 65. Multisynth2 ParametersBitD7D6D5D4

Seite 44 - 44 Preliminary Rev. 0.95

Si5351A/B/CPreliminary Rev. 0.95 49Reset value = xxxx xxxxReset value = xxxx xxxxRegister 68. Multisynth3 ParametersBitD7D6D5D4D3D2D1D0Name R3_DIV[2:0

Seite 45 - Preliminary Rev. 0.95 45

Si5351A/B/CPreliminary Rev. 0.95 5Table 3. AC Characteristics(VDD= 2.5 V ±10%, or 3.3 V ±10%, TA= –40 to 85 °C)Parameter Symbol Test Condition Min Typ

Seite 46 - 46 Preliminary Rev. 0.95

Si5351A/B/C50 Preliminary Rev. 0.95Reset value = xxxx xxxxReset value = xxxx xxxxReset value = xxxx xxxxRegister 70. Multisynth3 ParametersBitD7D6D5D4

Seite 47 - Preliminary Rev. 0.95 47

Si5351A/B/CPreliminary Rev. 0.95 51Reset value = xxxx xxxxReset value = xxxx xxxxReset value = xxxx xxxxRegister 73. Multisynth3 ParametersBitD7D6D5D4

Seite 48 - 48 Preliminary Rev. 0.95

Si5351A/B/C52 Preliminary Rev. 0.95Reset value = xxxx xxxxReset value = xxxx xxxxRegister 76. Multisynth4 ParametersBitD7D6D5D4D3D2D1D0Name R4_DIV[2:0

Seite 49 - Preliminary Rev. 0.95 49

Si5351A/B/CPreliminary Rev. 0.95 53Reset value = xxxx xxxxReset value = xxxx xxxxReset value = xxxx xxxxRegister 78. Multisynth4 ParametersBitD7D6D5D4

Seite 50 - 50 Preliminary Rev. 0.95

Si5351A/B/C54 Preliminary Rev. 0.95Reset value = xxxx xxxxReset value = xxxx xxxxReset value = xxxx xxxxRegister 81. Multisynth4 ParametersBitD7D6D5D4

Seite 51 - Preliminary Rev. 0.95 51

Si5351A/B/CPreliminary Rev. 0.95 55Reset value = xxxx xxxxReset value = xxxx xxxxRegister 84. Multisynth5 ParametersBitD7D6D5D4D3D2D1D0Name R5_DIV[2:0

Seite 52 - 52 Preliminary Rev. 0.95

Si5351A/B/C56 Preliminary Rev. 0.95Reset value = xxxx xxxxReset value = xxxx xxxxReset value = xxxx xxxxRegister 86. Multisynth5 ParametersBitD7D6D5D4

Seite 53 - Preliminary Rev. 0.95 53

Si5351A/B/CPreliminary Rev. 0.95 57Reset value = xxxx xxxxReset value = xxxx xxxxReset value = xxxx xxxxRegister 89. Multisynth5 ParametersBitD7D6D5D4

Seite 54 - 54 Preliminary Rev. 0.95

Si5351A/B/C58 Preliminary Rev. 0.95Reset value = xxxx xxxxRegister 92. Clock 6 and 7 Output DividerBitD7D6D5D4D3D2D1D0Name R7_DIV[2:0] R6_DIV[2:0]Type

Seite 55 - Preliminary Rev. 0.95 55

Si5351A/B/CPreliminary Rev. 0.95 59Reset value = 0000 0000Reset value = 0000 0000Reset value = 0000 0000 Register 165. CLK0 Initial Phase OffsetBitD7D

Seite 56 - 56 Preliminary Rev. 0.95

Si5351A/B/C6 Preliminary Rev. 0.95Table 5. Output Clock Characteristics(VDD= 2.5 V ±10%, or 3.3 V ±10%, TA=–40 to 85°C)Parameter Symbol Test Condition

Seite 57 - Preliminary Rev. 0.95 57

Si5351A/B/C60 Preliminary Rev. 0.95Reset value = 0000 0000Reset value = 0000 0000Reset value = 0000 0000 Register 168. CLK3 Initial Phase OffsetBitD7D

Seite 58 - 58 Preliminary Rev. 0.95

Si5351A/B/CPreliminary Rev. 0.95 61Reset value = 0000 0000Reset value = 11xx xxxx Register 177. PLL ResetBitD7D6D5D4D3D2D1D0NamePLLB_RST PLLA_RSTTypeR

Seite 59

Si5351A/B/C62 Preliminary Rev. 0.959. Si5351A Pin Descriptions (20-Pin QFN, 24-Pin QSOP)Table 10. Si5351A Pin DescriptionsPin NamePin NumberPin Type

Seite 60

Si5351A/B/CPreliminary Rev. 0.95 6310. Si5351B Pin Descriptions (20-Pin QFN, 24-Pin QSOP)Table 11. Si5351B Pin DescriptionsPin NamePin NumberPin Type

Seite 61

Si5351A/B/C64 Preliminary Rev. 0.9511. Si5351C Pin Descriptions (20-Pin QFN, 24-Pin QSOP)Table 12. Si5351C Pin DescriptionsPin NamePin NumberPin Type

Seite 62 - 62 Preliminary Rev. 0.95

Si5351A/B/CPreliminary Rev. 0.95 6512. Si5351A Pin Descriptions (10-Pin MSOP)Table 13. Si5351A 10-MSOP Pin DescriptionsPin NamePin NumberPin Type* Fu

Seite 63 - Preliminary Rev. 0.95 63

Si5351A/B/C66 Preliminary Rev. 0.9513. Ordering InformationFigure 19. Device Part NumbersAn evaluation kit containing ClockBuilder Desktop software a

Seite 64 - 64 Preliminary Rev. 0.95

Si5351A/B/CPreliminary Rev. 0.95 6714. Package Outline (24-Pin QSOP)Table 14. 24-QSOP Package DimensionsDimension Min Nom MaxA——1.75A1 0.10 — 0.25b 0

Seite 65 - Preliminary Rev. 0.95 65

Si5351A/B/C68 Preliminary Rev. 0.9515. Package Outline (20-Pin QFN)Table 15. Package DimensionsDimension Min Nom MaxA 0.800.850.90A1 0.00 0.02 0.05b

Seite 66 - 66 Preliminary Rev. 0.95

Si5351A/B/CPreliminary Rev. 0.95 6916. Package Outline (10-Pin MSOP)Table 16. 24-QSOP Package DimensionsDimension Min Nom MaxA——1.10A1 0.00 — 0.15A2

Seite 67

Si5351A/B/CPreliminary Rev. 0.95 7Table 7. I2C Specifications (SCL,SDA)1ParameterSymbol Test Condition Standard Mode100 kbpsFast Mode400 kbpsUnitMin M

Seite 68

Si5351A/B/C70 Preliminary Rev. 0.95DOCUMENT CHANGE LISTRevision 0.1 to Revision 0.9 Updated max output frequency. Updated kV values in Table 3 on pa

Seite 69

Si5351A/B/CPreliminary Rev. 0.95 71NOTES:

Seite 70 - 70 Preliminary Rev. 0.95

Si5351A/B/C72 Preliminary Rev. 0.95CONTACT INFORMATIONSilicon Laboratories Inc.400 West Cesar ChavezAustin, TX 78701Tel: 1+(512) 416-8500Fax: 1+(512)

Seite 71 - Preliminary Rev. 0.95 71

Si5351A/B/C8 Preliminary Rev. 0.95Table 9. Absolute Maximum Ratings1Parameter Symbol Test Condition Value UnitDC Supply Voltage VDD_max–0.5 to 3.8 VIn

Seite 72 - Silicon Laboratories Inc

Si5351A/B/CPreliminary Rev. 0.95 92. Detailed Block DiagramsFigure 1. Block Diagrams of 3-Output and 8-Output Si5351A DevicesPLLBPLLASDASCLOSCXAXBVDD

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