Silicon Laboratories C8051F340 Bedienungsanleitung Seite 194
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17.1. Supporting Documents
It is assumed the reader is familiar with or has access to the following supporting documents:
1. The I2C-Bus and How to Use It (including specifications), Philips Semiconductor.
2. The I2C-Bus Specification -- Version 2.0, Philips Semiconductor.
3. System Management Bus Specification -- Version 1.1, SBS Implementers Forum.
17.2. SMBus Configuration
Figure 17.2 shows a typical SMBus configuration. The SMBus specification allows any recessive voltage
between 3.0 V and 5.0 V; different devices on the bus may operate at different voltage levels. The bi-direc-
tional SCL (serial clock) and SDA (serial data) lines must be connected to a positive power supply voltage
through a pull-up resistor or similar circuit. Every device connected to the bus must have an open-drain or
open-collector output for both the SCL and SDA lines, so that both are pulled high (recessive state) when
the bus is free. The maximum number of devices on the bus is limited only by the requirement that the rise
and fall times on the bus not exceed 300
ns and 1000 ns, respectively.
Figure 17.2. Typical SMBus Configuration
17.3. SMBus Operation
Two types of data transfers are possible: data transfers from a master transmitter to an addressed slave
receiver (WRITE), and data transfers from an addressed slave transmitter to a master receiver (READ).
The master device initiates both types of data transfers and provides the serial clock pulses on SCL. The
SMBus interface may operate as a master or a slave, and multiple master devices on the same bus are
supported. If two or more masters attempt to initiate a data transfer simultaneously, an arbitration scheme
is employed with a single master always winning the arbitration. Note that it is not necessary to specify one
device as the Master in a system; any device who transmits a START and a slave address becomes the
master for the duration of that transfer.
A typical SMBus transaction consists of a START condition followed by an address byte (Bits7-1: 7-bit
slave address; Bit0: R/W direction bit), one or more bytes of data, and a STOP condition. Each byte that is
received (by a master or slave) must be acknowledged (ACK) with a low SDA during a high SCL (see
Figure 17.3). If the receiving device does not ACK, the transmitting device will read a NACK (not acknowl-
edge), which is a high SDA during a high SCL.
VDD = 5V
Master
Device
Slave
Device 1
Slave
Device 2
VDD = 3V VDD = 5V VDD = 3V
SD
A
SCL
- C8051F340/1/2/3/4/5/6/7 1
- Rev. 0.5 19 19
- 20 Rev. 0.5 20
- 1.1.1. Fully 8051 Compatible 21
- 1.1.2. Improved Throughput 21
- 1.1.3. Additional Features 21
- Microcontroller 22
- C8051F340/1/4/5 36
- Top View 36
- 5.3.1. Starting a Conversion 45
- 5.3.2. Tracking Modes 46
- 9.2.1. Program Memory 79
- 9.2.2. Data Memory 80
- 9.2.5. Stack 80
- 9.2.7. Register Descriptions 85
- 9.3.2. External Interrupts 87
- 9.3.3. Interrupt Priorities 88
- 9.3.4. Interrupt Latency 88
- 9.4.1. Idle Mode 96
- 9.4.2. Stop Mode 96
- 12.1.2. Flash Erase Procedure 109
- 12.1.3. Flash Write Procedure 110
- 13.1.1. 16-Bit MOVX Example 117
- 13.1.2. 8-Bit MOVX Example 117
- 13.6.1. Internal XRAM Only 124
- 13.6.4. External Only 125
- 13.7.1. Non-multiplexed Mode 127
- 13.7.2. Multiplexed Mode 130
- 14.3.3. External RC Example 140
- 14.5.2. USB Clock Selection 143
- 16.5.1. FIFO Split Mode 171
- 16.5.2. FIFO Double Buffering 172
- 16.5.1. FIFO Access 172
- 17.3.1. Arbitration 195
- 17.3.2. Clock Low Extension 196
- 17.3.3. SCL Low Timeout 196
- 17.4.3. Data Register 204
- 17.5.2. Master Receiver Mode 206
- 17.5.3. Slave Receiver Mode 207
- 18.2.1. 8-Bit UART 213
- 18.2.2. 9-Bit UART 214
- 19.3.1. Data Transmission 222
- 19.3.2. Data Reception 222
- 20.1.3. Serial Clock (SCK) 230
- 20.1.4. Slave Select (NSS) 230
- 266 Rev. 0.5 266
- Rev. 0.5 267 267
- 268 Rev. 0.5 268
- 22.2.4. Frequency Output Mode 269
- 270 Rev. 0.5 270
- Rev. 0.5 271 271
- WDT updates are performed 272
- PCA clocks) by 272
- 22.3.2. Watchdog Timer Usage 273
- 23.2. C2 Pin Sharing 281
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