Silicon Laboratories Stepper Machine Spezifikationen Seite 168
- Seite / 204
- Inhaltsverzeichnis
- LESEZEICHEN
- C8051F330/1 1
- Rev. 1.1 15 15
- 16 Rev. 1.1 16
- 1.1.1. Fully 8051 Compatible 17
- 1.1.2. Improved Throughput 17
- 1.1.3. Additional Features 18
- TOP VIEW 30
- 5.3.1. Starting a Conversion 38
- 5.3.2. Tracking Modes 39
- 9.2.1. Program Memory 73
- 9.2.2. Data Memory 74
- 9.2.5. Stack 74
- 9.2.7. Register Descriptions 78
- 9.3.2. External Interrupts 82
- 9.3.3. Interrupt Priorities 82
- 9.3.4. Interrupt Latency 82
- 9.4.1. Idle Mode 89
- 9.4.2. Stop Mode 89
- 11.1.2. FLASH Erase Procedure 97
- 11.1.3. FLASH Write Procedure 98
- 13.3.2. External RC Example 111
- 15.3.1. Arbitration 129
- 15.3.2. Clock Low Extension 130
- 15.3.3. SCL Low Timeout 130
- 15.4.3. Data Register 138
- 15.5.2. Master Receiver Mode 140
- 15.5.3. Slave Receiver Mode 141
- 16.2.1. 8-Bit UART 147
- 16.2.2. 9-Bit UART 148
- 17.1.3. Serial Clock (SCK) 156
- 17.1.4. Slave Select (NSS) 156
- 18.2. Timer 2 177
- 19.2.4. Frequency Output Mode 191
- 19.3.2. Watchdog Timer Usage 195
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