Silicon Laboratories SI5324 Betriebsanweisung Seite 1

AC701 Evaluation Board for the Artix-7 FPGAUser GuideUG952 (v1.1) January 30, 2013

10 www.xilinx.com AC701 Evaluation BoardUG952 (v1.1) January 30, 2013Chapter 1: AC701 Evaluation Board FeaturesThe default mode setting is M[2:0] = 0

Appendix D: Board Setup100 www.xilinx.com AC701 Evaluation BoardUG952 (v1.1) January 30, 20138. Slide the AC701 board power switch SW15 to the ON pos

AC701 Evaluation Board www.xilinx.com 101UG952 (v1.1) January 30, 2013Appendix EBoard SpecificationsDimensionsHeight 5.5 in (14.0 cm)Length 10.5 in (2

Appendix E: Board Specifications102 www.xilinx.com AC701 Evaluation BoardUG952 (v1.1) January 30, 2013

AC701 Evaluation Board www.xilinx.com 103UG952 (v1.1) January 30, 2013Appendix FAdditional ResourcesXilinx ResourcesFor support resources such as Answ

104 www.xilinx.com AC701 Evaluation BoardUG952 (v1.1) January 30, 2013Appendix F: Additional ResourcesUG475, 7 Series FPGAs Packaging and Pinout User

AC701 Evaluation Board www.xilinx.com 105UG952 (v1.1) January 30, 2013Appendix GRegulatory and Compliance InformationThis product is designed and test

106 www.xilinx.com AC701 Evaluation BoardUG952 (v1.1) January 30, 2013Appendix G: Regulatory and Compliance InformationEN 60950-1:2006, Information t

IMPORTANT NOTICE FOR TI REFERENCE DESIGNSTexas Instruments Incorporated ("TI") reference designs are solely intended to assist designers (“B

AC701 Evaluation Board www.xilinx.com 11UG952 (v1.1) January 30, 2013Feature DescriptionsI/O Voltage RailsIn addition to Bank 0, there are 8 I/O banks

12 www.xilinx.com AC701 Evaluation BoardUG952 (v1.1) January 30, 2013Chapter 1: AC701 Evaluation Board FeaturesDDR3 Memory Module[Figure 1-2, callout

AC701 Evaluation Board www.xilinx.com 13UG952 (v1.1) January 30, 2013Feature DescriptionsAA8 DDR3_D1 7 DQ1Y8 DDR3_D2 15 DQ2AB5 DDR3_D3 17 DQ3AA5 DDR3_

14 www.xilinx.com AC701 Evaluation BoardUG952 (v1.1) January 30, 2013Chapter 1: AC701 Evaluation Board FeaturesD1 DDR3_D33 131 DQ33E1 DDR3_D34 141 DQ

AC701 Evaluation Board www.xilinx.com 15UG952 (v1.1) January 30, 2013Feature DescriptionsAC4 DDR3_DM1 28 DM1AA3 DDR3_DM2 46 DM2U7 DDR3_DM3 63 DM3G1 DD

16 www.xilinx.com AC701 Evaluation BoardUG952 (v1.1) January 30, 2013Chapter 1: AC701 Evaluation Board FeaturesThe AC701 board DDR3 memory interface

AC701 Evaluation Board www.xilinx.com 17UG952 (v1.1) January 30, 2013Feature DescriptionsFlash memory on the AC701 board. For more details, see the Nu

18 www.xilinx.com AC701 Evaluation BoardUG952 (v1.1) January 30, 2013Chapter 1: AC701 Evaluation Board FeaturesSD Card Interface[Figure 1-2, callout

AC701 Evaluation Board www.xilinx.com 19UG952 (v1.1) January 30, 2013Feature DescriptionsTable 1-7: SDIO Connections to the FPGA U1 FPGA Pin NameSche

AC701 Evaluation Board www.xilinx.com UG952 (v1.1) January 30, 2013© Copyright 2012–2013 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spa

20 www.xilinx.com AC701 Evaluation BoardUG952 (v1.1) January 30, 2013Chapter 1: AC701 Evaluation Board FeaturesUSB JTAG Module[Figure 1-2, callout 5]

AC701 Evaluation Board www.xilinx.com 21UG952 (v1.1) January 30, 2013Feature DescriptionsClock GenerationThere are three clock sources available for t

22 www.xilinx.com AC701 Evaluation BoardUG952 (v1.1) January 30, 2013Chapter 1: AC701 Evaluation Board FeaturesSystem Clock Source[Figure 1-2, callou

AC701 Evaluation Board www.xilinx.com 23UG952 (v1.1) January 30, 2013Feature DescriptionsProgrammable User Clock Source[Figure 1-2, callout 7]The AC70

24 www.xilinx.com AC701 Evaluation BoardUG952 (v1.1) January 30, 2013Chapter 1: AC701 Evaluation Board FeaturesUser SMA Clock Input[Figure 1-2, callo

AC701 Evaluation Board www.xilinx.com 25UG952 (v1.1) January 30, 2013Feature DescriptionsGTP Clock MUXThe AC701 board FPGA U1 MGT Bank 213 has two clo

26 www.xilinx.com AC701 Evaluation BoardUG952 (v1.1) January 30, 2013Chapter 1: AC701 Evaluation Board Features125 MHz Clock Generator[Figure 1-2, ca

AC701 Evaluation Board www.xilinx.com 27UG952 (v1.1) January 30, 2013Feature DescriptionsJitter Attenuated Clock[Figure 1-2, callout 10]The AC701 boar

28 www.xilinx.com AC701 Evaluation BoardUG952 (v1.1) January 30, 2013Chapter 1: AC701 Evaluation Board FeaturesFMC HPC GBT ClocksThe FMC HPC connecto

AC701 Evaluation Board www.xilinx.com 29UG952 (v1.1) January 30, 2013Feature DescriptionsX-Ref Target - Figure 1-16Figure 1-16: MGT Clock MUX U3 Circ

AC701 Evaluation Board www.xilinx.com 3UG952 (v1.1) January 30, 2013Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

30 www.xilinx.com AC701 Evaluation BoardUG952 (v1.1) January 30, 2013Chapter 1: AC701 Evaluation Board FeaturesX-Ref Target - Figure 1-17Figure 1-17:

AC701 Evaluation Board www.xilinx.com 31UG952 (v1.1) January 30, 2013Feature DescriptionsGTP Transceivers[Figure 1-2, callout 11]The AC701 board provi

32 www.xilinx.com AC701 Evaluation BoardUG952 (v1.1) January 30, 2013Chapter 1: AC701 Evaluation Board FeaturesTable 1-12: GTP Interface Connections

AC701 Evaluation Board www.xilinx.com 33UG952 (v1.1) January 30, 2013Feature DescriptionsFor more information on the GTP transceivers see UG476, 7 Ser

34 www.xilinx.com AC701 Evaluation BoardUG952 (v1.1) January 30, 2013Chapter 1: AC701 Evaluation Board FeaturesPCIe lane width/size is selected via j

AC701 Evaluation Board www.xilinx.com 35UG952 (v1.1) January 30, 2013Feature DescriptionsTable 1-13 lists the SFP+ module RX and TX connections to the

36 www.xilinx.com AC701 Evaluation BoardUG952 (v1.1) January 30, 2013Chapter 1: AC701 Evaluation Board FeaturesTable 1-14 lists the SFP+ module contr

AC701 Evaluation Board www.xilinx.com 37UG952 (v1.1) January 30, 2013Feature DescriptionsThe Ethernet connections from the XC7A200T at U1 to the 88E11

38 www.xilinx.com AC701 Evaluation BoardUG952 (v1.1) January 30, 2013Chapter 1: AC701 Evaluation Board FeaturesEthernet PHY Clock SourceA 25.00 MHz,

AC701 Evaluation Board www.xilinx.com 39UG952 (v1.1) January 30, 2013Feature DescriptionsRefer to the Marvell 88E1116R Alaska Gigabit Ethernet transce

4 www.xilinx.com AC701 Evaluation BoardUG952 (v1.1) January 30, 2013Appendix D: Board SetupInstalling the AC701 Board in a PC Chassis . . . . . . . .

40 www.xilinx.com AC701 Evaluation BoardUG952 (v1.1) January 30, 2013Chapter 1: AC701 Evaluation Board FeaturesRefer to the Silicon Labs website for

AC701 Evaluation Board www.xilinx.com 41UG952 (v1.1) January 30, 2013Feature DescriptionsFigure 1-23 shows the HDMI codec circuit.X-Ref Target - Figur

42 www.xilinx.com AC701 Evaluation BoardUG952 (v1.1) January 30, 2013Chapter 1: AC701 Evaluation Board FeaturesTable 1-19 lists the connections betwe

AC701 Evaluation Board www.xilinx.com 43UG952 (v1.1) January 30, 2013Feature DescriptionsTable 1-20 lists the connections between the codec and the HD

44 www.xilinx.com AC701 Evaluation BoardUG952 (v1.1) January 30, 2013Chapter 1: AC701 Evaluation Board FeaturesThe AC701 board base board uses a male

AC701 Evaluation Board www.xilinx.com 45UG952 (v1.1) January 30, 2013Feature DescriptionsTable 1-21 lists the connections between the FPGA and the LCD

46 www.xilinx.com AC701 Evaluation BoardUG952 (v1.1) January 30, 2013Chapter 1: AC701 Evaluation Board Features. Table 1-22 lists the address for eac

AC701 Evaluation Board www.xilinx.com 47UG952 (v1.1) January 30, 2013Feature DescriptionsUser I/O[Figure 1-2, callout 21 - 25]The AC701 board provides

48 www.xilinx.com AC701 Evaluation BoardUG952 (v1.1) January 30, 2013Chapter 1: AC701 Evaluation Board FeaturesUser GPIO LEDs[Figure 1-2, callout 21]

AC701 Evaluation Board www.xilinx.com 49UG952 (v1.1) January 30, 2013Feature DescriptionsFigure 1-30 shows the user CPU_RESET pushbutton switch circui

AC701 Evaluation Board www.xilinx.com 5UG952 (v1.1) January 30, 2013Chapter 1AC701 Evaluation Board FeaturesOverviewThe AC701 evaluation board for the

50 www.xilinx.com AC701 Evaluation BoardUG952 (v1.1) January 30, 2013Chapter 1: AC701 Evaluation Board FeaturesUser SMA Connectors[Figure 1-2, callou

AC701 Evaluation Board www.xilinx.com 51UG952 (v1.1) January 30, 2013Feature DescriptionsTable 1-24 lists the GPIO Connections to FPGA U1.Table 1-24:

52 www.xilinx.com AC701 Evaluation BoardUG952 (v1.1) January 30, 2013Chapter 1: AC701 Evaluation Board FeaturesSwitches[Figure 1-2, callout 26 - 27]T

AC701 Evaluation Board www.xilinx.com 53UG952 (v1.1) January 30, 2013Feature DescriptionsFigure 1-36 shows the simplified diagram of the power connect

54 www.xilinx.com AC701 Evaluation BoardUG952 (v1.1) January 30, 2013Chapter 1: AC701 Evaluation Board FeaturesConfiguration Mode Switch SW1The AC701

AC701 Evaluation Board www.xilinx.com 55UG952 (v1.1) January 30, 2013Feature DescriptionsThe Samtec connector system is rated for signaling speeds up

56 www.xilinx.com AC701 Evaluation BoardUG952 (v1.1) January 30, 2013Chapter 1: AC701 Evaluation Board FeaturesA19 NC NA B20 FMC1_HPC_GBTCLK1_M2C_P U

AC701 Evaluation Board www.xilinx.com 57UG952 (v1.1) January 30, 2013Feature DescriptionsD33 FMC1_HPC_TMS_BUF U19.15D34 NC NAD35 GND NAD36 VCC3V3 NAD3

58 www.xilinx.com AC701 Evaluation BoardUG952 (v1.1) January 30, 2013Chapter 1: AC701 Evaluation Board FeaturesG2 FMC1_HPC_CLK1_M2C_P H1 NC NAG3 FMC1

AC701 Evaluation Board www.xilinx.com 59UG952 (v1.1) January 30, 2013Feature DescriptionsAC701 Board Power SystemThe AC701 board hosts a power system

6 www.xilinx.com AC701 Evaluation BoardUG952 (v1.1) January 30, 2013Chapter 1: AC701 Evaluation Board Features• Gen1 4-lane (x4)• Gen2 4-lane (x4)• S

60 www.xilinx.com AC701 Evaluation BoardUG952 (v1.1) January 30, 2013Chapter 1: AC701 Evaluation Board FeaturesThe UCD90120A device is configured by

AC701 Evaluation Board www.xilinx.com 61UG952 (v1.1) January 30, 2013Feature DescriptionsFigure 1-40 shows the power system for UCD90120A U8 controlle

62 www.xilinx.com AC701 Evaluation BoardUG952 (v1.1) January 30, 2013Chapter 1: AC701 Evaluation Board FeaturesTable 1-28 shows the AC701 TI power sy

AC701 Evaluation Board www.xilinx.com 63UG952 (v1.1) January 30, 2013Feature DescriptionsFigure 1-41 shows the power system for UCD90120A U9 controlle

64 www.xilinx.com AC701 Evaluation BoardUG952 (v1.1) January 30, 2013Chapter 1: AC701 Evaluation Board FeaturesThe TPS84K and LMZ22000 family adjusta

AC701 Evaluation Board www.xilinx.com 65UG952 (v1.1) January 30, 2013Feature DescriptionsFigure 1-42 shows the XADC external multiplexer block diagram

66 www.xilinx.com AC701 Evaluation BoardUG952 (v1.1) January 30, 2013Chapter 1: AC701 Evaluation Board FeaturesSee Tables Table 1-29 and Table 1-30 w

AC701 Evaluation Board www.xilinx.com 67UG952 (v1.1) January 30, 2013Feature DescriptionsPower Management[Figure 1-2, callout 30]The AC701 board uses

68 www.xilinx.com AC701 Evaluation BoardUG952 (v1.1) January 30, 2013Chapter 1: AC701 Evaluation Board FeaturesX-Ref Target - Figure 1-43Figure 1-43:

AC701 Evaluation Board www.xilinx.com 69UG952 (v1.1) January 30, 2013Feature DescriptionsThe AC701 board core and auxiliary voltages are listed in Tab

AC701 Evaluation Board www.xilinx.com 7UG952 (v1.1) January 30, 2013Feature Descriptionshttp://www.xilinx.com/AC701Caution! The AC701 board can be da

70 www.xilinx.com AC701 Evaluation BoardUG952 (v1.1) January 30, 2013Chapter 1: AC701 Evaluation Board Featuresinternally ORs these PG conditions tog

AC701 Evaluation Board www.xilinx.com 71UG952 (v1.1) January 30, 2013Feature DescriptionsIn this VCCO_VADJ off mode, the user can control when to turn

72 www.xilinx.com AC701 Evaluation BoardUG952 (v1.1) January 30, 2013Chapter 1: AC701 Evaluation Board FeaturesXADC Header[Figure 1-2, callout 31]7 s

AC701 Evaluation Board www.xilinx.com 73UG952 (v1.1) January 30, 2013Feature DescriptionsThe AC701 board supports both the internal FPGA sensor measur

74 www.xilinx.com AC701 Evaluation BoardUG952 (v1.1) January 30, 2013Chapter 1: AC701 Evaluation Board FeaturesTable 1-35 describes the XADC header J

AC701 Evaluation Board www.xilinx.com 75UG952 (v1.1) January 30, 2013Configuration OptionsConfiguration OptionsThe FPGA on the AC701 board can be conf

76 www.xilinx.com AC701 Evaluation BoardUG952 (v1.1) January 30, 2013Chapter 1: AC701 Evaluation Board FeaturesFigure 1-48 shows the QSPI U7 configur

AC701 Evaluation Board www.xilinx.com 77UG952 (v1.1) January 30, 2013Appendix ADefault Switch and Jumper SettingsUser GPIO DIP Switch SW2See Figure 1-

Appendix A: Default Switch and Jumper Settings78 www.xilinx.com AC701 Evaluation BoardUG952 (v1.1) January 30, 2013Configuration DIP Switch SW1See Fi

Default Jumper SettingsAC701 Evaluation Board www.xilinx.com 79UG952 (v1.1) January 30, 2013Default Jumper SettingsThe AC701 board default jumper conf

8 www.xilinx.com AC701 Evaluation BoardUG952 (v1.1) January 30, 2013Chapter 1: AC701 Evaluation Board FeaturesX-Ref Target - Figure 1-2Figure 1-2: A

Appendix A: Default Switch and Jumper Settings80 www.xilinx.com AC701 Evaluation BoardUG952 (v1.1) January 30, 2013

AC701 Evaluation Board www.xilinx.com 81UG952 (v1.1) January 30, 2013Appendix BVITA 57.1 FMC Connector PinoutsFigure B-1 shows the pinout of the FPGA

Appendix B: VITA 57.1 FMC Connector Pinouts82 www.xilinx.com AC701 Evaluation BoardUG952 (v1.1) January 30, 2013

AC701 Evaluation Board www.xilinx.com 83UG952 (v1.1) January 30, 2013Appendix CMaster Constraints File ListingTheAC701 board master Xilinx® design con

Appendix C: Master Constraints File Listing84 www.xilinx.com AC701 Evaluation BoardUG952 (v1.1) January 30, 2013set_property IOSTANDARD LVCMOS25 [get

AC701 Board XDC File ListingAC701 Evaluation Board www.xilinx.com 85UG952 (v1.1) January 30, 2013set_property PACKAGE_PIN AD17 [get_ports FMC1_HPC_HA1

Appendix C: Master Constraints File Listing86 www.xilinx.com AC701 Evaluation BoardUG952 (v1.1) January 30, 2013set_property IOSTANDARD LVCMOS18 [get

AC701 Board XDC File ListingAC701 Evaluation Board www.xilinx.com 87UG952 (v1.1) January 30, 2013set_property PACKAGE_PIN U17 [get_ports PHY_RXD0]set_

Appendix C: Master Constraints File Listing88 www.xilinx.com AC701 Evaluation BoardUG952 (v1.1) January 30, 2013set_property IOSTANDARD LVCMOS33 [get

AC701 Board XDC File ListingAC701 Evaluation Board www.xilinx.com 89UG952 (v1.1) January 30, 2013set_property PACKAGE_PIN L14 [get_ports FMC1_HPC_LA19

AC701 Evaluation Board www.xilinx.com 9UG952 (v1.1) January 30, 2013Feature DescriptionsArtix-7 FPGA[Figure 1-2, callout 1]The AC701 board is populate

Appendix C: Master Constraints File Listing90 www.xilinx.com AC701 Evaluation BoardUG952 (v1.1) January 30, 2013set_property IOSTANDARD LVCMOS25 [get

AC701 Board XDC File ListingAC701 Evaluation Board www.xilinx.com 91UG952 (v1.1) January 30, 2013set_property PACKAGE_PIN A17 [get_ports FMC1_HPC_LA10

Appendix C: Master Constraints File Listing92 www.xilinx.com AC701 Evaluation BoardUG952 (v1.1) January 30, 2013set_property IOSTANDARD LVCMOS25 [get

AC701 Board XDC File ListingAC701 Evaluation Board www.xilinx.com 93UG952 (v1.1) January 30, 2013set_property PACKAGE_PIN AB4 [get_ports DDR3_D14]set_

Appendix C: Master Constraints File Listing94 www.xilinx.com AC701 Evaluation BoardUG952 (v1.1) January 30, 2013set_property IOSTANDARD SSTL15 [get_p

AC701 Board XDC File ListingAC701 Evaluation Board www.xilinx.com 95UG952 (v1.1) January 30, 2013set_property PACKAGE_PIN U2 [get_ports DDR3_ODT1]set_

Appendix C: Master Constraints File Listing96 www.xilinx.com AC701 Evaluation BoardUG952 (v1.1) January 30, 2013set_property IOSTANDARD SSTL15 [get_p

AC701 Board XDC File ListingAC701 Evaluation Board www.xilinx.com 97UG952 (v1.1) January 30, 2013set_property PACKAGE_PIN E2 [get_ports DDR3_D35]set_p

Appendix C: Master Constraints File Listing98 www.xilinx.com AC701 Evaluation BoardUG952 (v1.1) January 30, 2013

AC701 Evaluation Board www.xilinx.com 99UG952 (v1.1) January 30, 2013Appendix D Board SetupInstalling the AC701 Board in a PC ChassisInstallation of t